ΜΔΕ664 Σχεδίαση Ασύγχρονων Κυκλωμάτων

ΜΔΕ664 Σχεδίαση Ασύγχρονων Κυκλωμάτων

Π.Μ.Σ.Επιστήμη & Τεχνολογία Ηλεκτρολόγου Μηχανικού & Μηχανικού Υπολογιστών
Γνωστικός ΤομέαςOμάδα Τεχνολογιών Υλικού και Αρχιτεκτονικής των Υπολογιστών (ΥΑ)
ΕξάμηνοΕαρινό
Τύπος ΜαθήματοςΕπιλογής
Μονάδες ECTS7,5
Εβδομαδιαίες Ώρες Διδασκαλίας3
Συνιστώμενα

Βασικές Γνώσεις Ψηφιακής Σχεδίασης

Σελίδα Μαθήματοςhttps://courses.e-ce.uth.gr/CE664/
Επιστημονικός
Υπεύθυνος

Σωτηρίου ΧρήστοςΣωτηρίου Χρήστος, Καθηγητής
E-mail: chsotiriou@uth.gr

Συγγράμματα
  • Principles of Asynchronous Circuit Design: A Systems Perspective (European Low-Power Initiative for Electronic System Design) , Jens Sparso and Steve Furber, ISBN-10: 1441949364, October, 2010.
  • Asynchronous Circuit Design , Chris J. Myers, ISBN-10: 047141543X, Wiley Interscience, 2001.
  • A Designer’s Guide to Asynchronous VLSI , Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti, ISBN-10: 0521872448, Cambridge University Press, March 2010.

Δημοσιεύσεις:

1. S. Nowick and M. Singh, Asynchronous Design – Part 1: Overview and Recent Advances , IEEE Design and Test, Volume 32, Issue 3, pp. 5-18, June 2015.
2. S. Nowick and M. Singh, Asynchronous Design – Part 2: Systems and Methodologies , IEEE Design and Test, Volume 32, Issue 3, pp. 19-28, June 2015.
3. Sutherland, Micropipelines , Communications of the ACM, Volume 32, Issue 6, pp. 720-738, June 1989
4. M. Singh and S. Nowick, MOUSETRAP: High-Speed Transition Signaling Asynchronous Pipelines , IEEE Transactions on VLSI Systems, Volume 15, Issue 6, pp. 684-698, June 2007.
5. Modular Design of Asynchronous Circuits Defined by Graphs, , IEEE Transactions on Computers, Volume C-26, No. 8, 1977.
6. L. Hollaar, Direct Implementation of Asynchronous Control Units , IEEE Transactions on Computers, Volume C-31, Issue 12, pp. 1133-1141, 1982.
7. Christos P. Sotiriou, Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow , Proceedings of 39th DAC, pp. 415-418, 2002.
8. Four-Phase Micropipeline Latch Control Circuits, Four-Phase Micropipeline Latch Control Circuits , IEEE Transactions on VLSI Systems, Volume 4, Issue 2, pp. 247-253, 1996.
9. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou, Handshake Protocols for De-synchronization , Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, pp. 149-158, 2004.
10. J. Cortadella, A. Kondratyev, L. Lavagno and C. P. Sotiriou, Desynchronization: Synthesis of Asynchronous Circuits from Synchronous Specifications , IEEE Transactions on CAD, Volume 25, No. 10, pp 1904-1921, 2006.
11. N. Penmetsa, C. P. Sotiriou and S. K. Lim, Low Power Monolithic 3D IC Design of Asynchronous AES Core , Proceedings of the 21st International Symposium on Asynchronous Circuits and Systems, pp. 93-99, 2015.
12. E. B. Eichelberger, Hazard Detection in Combinational and Sequential Switching Circuits , IBM Journal of Research and Development, Volume 9, Issue 2, pp. 90-99, 1965
13. S. H. Unger, Hazards, Critical Races, and Metastability , IEEE Transactions on Computers, Volume 44, Issue 6, pp. 754-768, 1995.
14. F. Shi and Y. Makris, SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits , Proceedings of the ITC 2004, pp. 597-606, 2004.
15. Y. Xu and K. S. Stevens, Automatic Synthesis of Computation Interference Constraints for Relative Timing Verification , Proceedings of ICCD 2009, pp. 16-22, 2009.
16. J. Sparso, J. Staunstrup, M. D. Sorensen, Design of delay insensitive circuits using multi-ring structures , Proceedings of EURO-DAC 1996, pp. 15-20, 1996.
17. M. Linthart, K. Fant, R. Smith, A. Taubin and A. Kondratyev, Asynchronous Design Using Commercial HDL Synthesis Tools , Proceedings of ASYNC 2000, pp. 114-125, 2000.
18. Kondratyev, K. Lwin, Design of Asynchronous Circuits by Synchronous CAD Tools , Proceedings of the 39th DAC, pp. 411-414, 2002.
19. J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou, Coping with the Variability of Combinational Logic Delays , Proceedings of ICCD 2004, pp. 505-508, 2004.
20. T. Murata, Petri Nets: Properties, Analysis and Applications , Proceedings of the IEEE, Volume 77, Issue 4, pp. 541-580, 1989.
21. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, A Region-Based Theory for State Assignment in Speed-Independent Circuits , IEEE Transactions on CAD, Volume 16, Issue 8, pp. 793-812, 2002.
22. R. Cordone, L. Ferrarini and L. Piroddi, Some Results on the Computation of Minimal Siphons in Petri Nets> , Proceedings of 42nd IEEE Conference on Decision and Control, Volume 4, pp. 3754-3759, 2003.
23. J. Esparza, E. Best, M. Silva, Minimal Deadlocks in Free Choice Nets , Universitat Hildesheim. Institut fur Informatik, 1989.
24. P. Kemper and F. Bause, An Efficient Polynomial-Time Algorithm to Decide Liveness and Boundedness of Free-Choice Nets , Application and Theory of Petri Nets 1992. Springer Berlin Heidelberg, pp. 263-278m, 1992.
25. P. M. Mattheakis, C. P. Sotiriou and P. A. Beerel, A Polynomial Time Flow For Implementing Free-Choice Petri-Nets , ICCD 2012, pp. 227-234, 2012.
26. C. V. Ramamoorthy and G. S. Ho, Performance Evaluation of Asynchronous Concurrent Systems Using Petri Nets , IEEE Transactions on Software Engineering, Volume SE-6, Issue 5, pp. 440-449, 1980
27. J. Maggott, Performance Evaluation of Concurrent Systems using Petri Nets , Information Processing Letters 18, p. 7-13, 1984.
28. R. M. Karp, A Characterization of the Minimum Cycle Mean in a Digraph , Discrete Mathematics, Volume 23, Issue 3, pp. 309-311, 1978.
29. H. Hulgaard, S. Burns, T. Amon and G. Borriello, An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems , IEEE Transactions on Computers, Volume 44, Issue 11, 2002.
30. S. Kim and P. Beerel, Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm , IEEE Transactions on CAD, Volume 25, Issue 3, pp. 389-402, 2006