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| Dimitrios Garyfallou, Academic Teaching Experience | |
|---|---|
| Diploma | Computer & Communication Engineering, University of Thessaly |
| Ph.D. | Electrical and Computer Engineering, University of Thessaly |
| Office | 314 |
| Office Hours | Tuesday 9:00-11:00 |
| Tel. | +30 24210 74972 |
| digaryfa@uth.gr | |
| Google Scholar | |
Thesis:
Dimitrios Garyfallou, “Novel techniques for timing analysis of VLSI circuits in advanced technology nodes”. Ph.D. Thesis. Department of Electrical and Computer Engineering, University of Thessaly, August 2021.
Dimitrios Garyfallou, “Development and optimization of a combinatorial multigrid algorithm for large scale circuit simulation on massively parallel architectures”. M.Sc. Thesis. Department of Electrical and Computer Engineering, University of Thessaly, November 2015.
Dimitrios Garyfallou, “Simulation of large-scale circuits with Steiner node preconditioners on parallel architectures”. Diploma Thesis. Department of Electrical and Computer Engineering, University of Thessaly, September 2014.
Conferences:
[C.18] Anastasis Vagenas, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “Advanced gate-level glitch modeling using ANNs”. ACM 61st Design Automation Conference (DAC), San Francisco, CA, 2024, pp. 1-6.
[C.17] Anastasis Vagenas, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “A learning-based method for performance optimization of timing analysis”. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Volos, 2024, pp. 1-4. (best paper award nomination).
[C.16] Christos Giamouzis, Dimitrios Garyfallou, Nestor Evmorfopoulos. “Low-rank balanced truncation of RLCk models via frequency-aware rational Krylov-based projection”. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Volos, 2024, pp 1-4.
[C.15] Christos Giamouzis, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion”. HETiA Emerging Tech Conference – Edge Intelligence (ETCEI), Volos, 2024.
[C.14] Achilleas Doumanis, Dimitrios Gerontitis, Dimitrios Garyfallou. “Accelerated Recurrent Neural Network Dynamics for Time-Varying Lyapunov Equation Solving”. 7th PAnhellenic Conference on Electronics and Telecommunications (PACET), Thessaloniki, 2024, pp. 1-6.
[C.13] Dimitrios Garyfallou et. al. “MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits”. HETiA Emerging Tech Conference – Edge Intelligence (ETCEI), Thessaloniki, 2023.
[C.12] Christos Giamouzis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor Evmorfopoulos. “Reduction of large-scale RLCK models via low-rank balanced truncation”. HETiA Emerging Tech Conference – Edge Intelligence (ETCEI), Thessaloniki, 2023.
[C.11] Georgios-Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor Evmorfopoulos, George Stamoulis. “Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis”. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Juan-Les-Pins, 2023, pp. 1-6.
[C.10] Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential”. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Funchal, 2023, pp. 1-4.
[C.9] Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential”. ACM 28th Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, 2023, pp. 1-6.
[C.8] Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, and George Stamoulis. “Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance”. ACM Great Lakes Symposium on VLSI 2022 (GLSVLSI), Irvine, CA, 2022, pp. 77–83.
[C.7] Olympia Axelou, Dimitrios Garyfallou, George Floros. “Frequency-limited reduction of RLCk circuits via second-order balanced truncation”. SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, Erfurt, 2021, pp. 1-4. (best paper award nomination).
[C.6] Chrysostomos Chatzigeorgiou, Dimitrios Garyfallou, George Floros, Nestor Evmorfopoulos, George Stamoulis. “Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models”. ACM 26th Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, 2021, pp. 773-778.
[C.5] Dimitrios Garyfallou, Ioannis Tsiokanos, Nestor Evmorfopoulos, Georgios Stamoulis, Georgios Karakonstantis. “Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation”. IEEE 21st International Symposium on Quality Electronic Design (ISQED), Santa Clara, 2020, pp. 225-230.
[C.4] Dimitrios Garyfallou, Charalampos Antoniadis, Nestor Evmorfopoulos, Georgios Stamoulis. “A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects”. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, 2019, pp. 89-92.
[C.3] Dimitrios Garyfallou, Nestor Evmorfopoulos, Georgios Stamoulis. “A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPUs”. International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, 2018, pp. 209-212.
[C.2] Dimitrios Garyfallou, Nestor Evmorfopoulos, Georgios Stamoulis. “Large Scale Circuit Simulation Exploiting Combinatorial Multigrid on Massively Parallel Architectures”. International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, 2018, pp. 1-4.
[C.1] Charalampos Antoniadis, Dimitrios Garyfallou, Nestor Evmorfopoulos, Georgios Stamoulis. “EVT-based Worst Case Delay Estimation Under Process Variation”. Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 1333-1338.
Journals:
[J.4] Anastasis Vagenas, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “TimeBoost: Accelerating timing analysis engines using XGBoost”. AEU - International Journal of Electronics and Communications, Elsevier. (invited).
[J.3] Georgios-Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor Evmorfopoulos, George Stamoulis. “A gate-level SER estimation tool with event-driven dynamic timing and SET height consideration”. IEEE Transactions on Device and Materials Reliability (TDMR), Nov 2024.
[J.2] Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor Evmorfopoulos, George Stamoulis. “Gate Delay Estimation with Library Compatible Current Source Models and Effective Capacitance”. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 29, N° 5, pp. 962–972, May 2021.
[J.1] Antonios N. Dadaliaris, Panagiotis Oikonomou, Maria G. Koziri, Evangelia Nerantzaki, Yannis Hatzaras, Dimitrios Garyfallou, Thanasis Loukopoulos, Georgios I. Stamoulis. “Heuristics to Augment the Performance of Tetris Legalization: Making a Fast but Inferior Method Competitive”. Journal Of Low Power Electronics, Vol. 13, N° 2, pp. 220–230, June 2017.
Preprints:
[PP.1] Pavlos Stoikos, Dimitrios Garyfallou, George Floros, Nestor Evmorfopoulos, George Stamoulis. “The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models”. arXiv:2204.02467, 2022.
Abstracts and posters:
[P.4] Anastasis Vagenas, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “Advanced gate-level glitch modeling using ANNs”. ACM 61st Design Automation Conference (DAC), Young Fellows, Poster Session, San Francisco, CA, 2024.
[P.3] Dimitrios Garyfallou. “Novel techniques for timing analysis of VLSI circuits in advanced technology nodes”. IEEE CEDA and ACM SIGDA Ph.D. Forum. Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, 2023.
[P.2] Dimitrios Garyfallou. “Novel techniques for timing analysis of VLSI circuits”. ACM SIGDA Ph.D. Forum. 28th Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, 2023.
[P.1] Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis. “VLSI Circuit Design and Optimization Under Voltage Drop Constraints Derived from an Extreme Value Theory Framework”. HiPEAC ACACES, Rome, 2018.