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      MLSysOps: Machine Learning for Autonomic System Operation in the Heterogeneous Edge-Cloud Continuum

      Scientific Responsible

      Spyros LalisSpyros Lalis, Professor
      E-mail: lalis@e-ce.uth.gr

      TitleMLSysOps: Machine Learning for Autonomic System Operation in the Heterogeneous Edge-Cloud Continuum
      Duration2023 – 2025
      Sitehttps://csl.e-ce.uth.gr/projects/mlsysops

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      Tel.+30 24210 74967, +30 24210 74934
      e-mailgece ΑΤ e-ce.uth.gr
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ECE219 Computer Organization & Design

Home » Studies » Undergraduate Studies » Undergraduate Courses » ECE219 Computer Organization & Design
    Subject AreaComputer Hardware and Architecture
    SemesterSemester 3 – Fall
    TypeRequired
    Teaching Hours5
    ECTS6
    Prerequisites
    • ECE115 Programming I
    • ECE119 Digital Design
    Course Sitehttps://courses.e-ce.uth.gr/ECE219/
    Course Director

    Nikolaos BellasNikolaos Bellas, Professor
    E-mail: nbellas@e-ce.uth.gr

    Course Instructor
    • Nikolaos Bellas, Professor
      E-mail: nbellas@e-ce.uth.gr
    • Description
    • Learning Outcomes

    Course curriculum follows:

    • High level description of a processor-based computer. Processing Units, registers, memory.
    • Introduction to Instruction Set Architecture (assembly language) with focus on MIPS assembly. Emphasis on assembly programming.
    • Support for Procedure Call Standards in ISAs. Stack. Application Binary Interfaces.
    • Exceptions/Interrupts in a processor.
    • Intel’s x86 Instruction Set Architecture and comparison between RISC and CISC architectures.
    • Data type representation in a computer. Integer and floating point computer arithmetic. Computer arithmetic operations such as addition, multiplication, division, etc.
    • Computer performance metrics.
    • Micro-architectural organization of a MIPS processor.
    • Implementation of a single-cycle MIPS processor. Data path and control unit.
    • Pipeline implementation of a MIPS processor. Limitations and Hazards (structural, data and control hazards). Data forwarding, stalling, and branch prediction.
    • Memory hierarchy and cache memories. Functionality and structure of cache memories.
    • Processor performance with cache memory hierarchy.
    • Virtual Memory
    • Introduction to hardware description languages such as Verilog. Design and implementation of processing elements using Verilog.

    This is an introductory course on the structure and functionality of modern computing systems. The curriculum introduces the students to the important concepts of instruction set architectures (ISA) as the basic interface between software and hardware implementation, and the microarchitectural implementation of a modern processing system.
    Students that have successfully concluded the course will:

    • have excellent knowledge of the functionality and organization of a modern processor.
    • She will understand basic concepts of ISAs (assembly language) and the interaction between assembly, high-level programming languages and processor hardware.
    • She will be able to develop advance programs in assembly language (MIPS assembly).
    • She will understand computer arithmetic, both integer and floating point and computer operations (addition, multiplication, division, etc.)
    • She will be able to analyze the performance of a processor and to understand the factors that determine performance in such a system.
    • She will be able to design, implement and simulate a processor using a Hardware Description Language such as Verilog.

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    Contact Info

    • Sekeri – Cheiden Str, Pedion Areos, Volos
    • +30 24210 74967
    • +30 24210 74934
    • Email: gece@e-ce.uth.gr

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