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      Hellenic Chips Competence Centre

      Scientific ResponsibleStamoulis GeorgiosStamoulis Georgios, Professor
      E-mail: georges@uth.gr
      TitleHellenic Chips Competence Centre
      Funding AgencyChips Joint Undertaking
      Budget326.350,00
      Duration01/06/2025 – 31/05/2029

      Αναλογικός Σχεδιασμός, Δοκιμές και Επαλήθευση

      Scientific ResponsiblePlessas FotiosPlessas Fotios, Professor
      E-mail: fplessas@uth.gr
      TitleΑναλογικός Σχεδιασμός, Δοκιμές και Επαλήθευση
      Funding AgencyNanoZeta Technologies ltd.
      Budget271.400,00
      Duration26/01/2021 – 25/01/2028

      DIGITAfrica: Towards a comprehensive pan-African research infrastructure in Digital Sciences

      Scientific ResponsibleKorakis AthanasiosKorakis Athanasios, Professor
      E-mail: korakis@uth.gr
      TitleDIGITAfrica: Towards a comprehensive pan-African research infrastructure in Digital Sciences
      Funding AgencyΕΥΡΩΠΑΪΚΗ ΕΝΩΣΗ
      Budget123.125,00
      Duration16/12/2024 – 31/12/2027

      List of Research Projects →

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      • Sekeri – Cheiden Str
        Pedion Areos, ECE Building
        383 34 Volos – Greece
      Tel.+30 24210 74967, +30 24210 74934
      e-mailgece ΑΤ uth.gr
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      PGS e-mailpgsec ΑΤ uth.gr
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ECE330 SoC CAD Lab

Home » Studies » Undergraduate Studies » Undergraduate Courses » ECE330 SoC CAD Lab
    Subject AreaComputer Hardware and Architecture
    SemesterSemester 6 – Spring
    TypeElective
    Teaching Hours4
    ECTS6
    Prerequisites
    • ECE119 Digital Design
    Recommended Courses
    • ECE333 Digital Systms Lab
    Course Sitehttp://eclass.uth.gr/eclass/courses/MHX219/
    Course Director

    Ioannis MountanosIoannis Mountanos, Associate Professor
    E-mail: jmoondan@uth.gr

    Course Instructor
    • Christos Sotiriou, Professor
      E-mail: chsotiriou@uth.gr
    • Description
    • Learning Outcomes

    The goals of the course include (1) the presentation and in-depth discussion of industrial design implementation and test methodologies for Application Specific Integrated Circuits (ASIC), (2) getting to grips with the relevant theoretical and practical issues, processes and flow standards, and (3) gaining practical experience actually using industrial ASIC design tools.

    In the course, industrial design and implementation tools are presented, which begin with the circuit in High Level Description (HDL) format, and produce a complete floorplanning and placement of the circuit in the form (GDSII) needed for delivery at a fab.

    The course syllabus will enable the student, upon its completion, to:

    • familiarize themselves with industrial flows for circuit design, from RTL to GDSII
    • be able to use industrial design tools as an experienced user, and to comprehend changes undergone by the circuit while optimized for area, performance or power consumption
    • gain insight into the design issues of timing, performance, power consumption, verification and test
    • become knowledgeable enough so as to be able to work as a junior VLSI engineer in an corporate environment using CAD tools

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    Contact Info

    • Sekeri – Cheiden Str, Pedion Areos, Volos
    • +30 24210 74967
    • +30 24210 74934
    • Email: gece@uth.gr

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