ECE333 Digital Systms Lab

• Revision of Digital Logic Fundamentals
  Binary Arithmetic, Digital Logic, Electrical Characteristics of Circuits
  Boolean Algebra, Combinational and Sequential Gates
  Flip-Flops and Latches, and their operation
  Finite State Machines
  Circuit Types
• Electronic Design Automation Flows
  EDA Flow Steps
  Hierarchical Design
  Abstraction Layers – Hardware Description Languages
• The Verilog Hardware Description Language
  Verilog particulars, Verilog Representation and Implementation
  Modules, Instances, Syntax and Time in Verilog
  Primitives, Modeling Styles, Language Conventions
  Number Representation, Operators, Variables and Types
  Assignments, Ports, Busses
  if/else, case statements, Synthesisability, Functional Test
  Sensitivity Lists, initial/always Blocks, Wire Assignments
  for/while loops, Parameters, Memory, Functions and Tasks
  Events, Delays, Dependencies between Parallel blocks
  Synthesisable Structures and Circuit Mapping
  Flip-Flops, Counters, Accumulators, Shifters, Multiplexers
  Encoders, Decoders, Adders, Comparators
  Edge Detector, D Latch, Synchronous/Asynchronous Memory
  FSM Descriptions in Verilog
• Arithmetic Circuits
  Half and Full Adder, Ripple-Carry Adder
  Look-Ahead Carry Adder, Carry Computation and Hierarchy
  Multiplication Algorithm, Shift and Add Multiplier
  Lookup Table Multiplier, Partial product Multiplier
  Division Algorithm, Comparison, Shift and Subtract
• Synchronisation and Metastability
  Synchronisation Scenarios, Vo/Vi Characteristic and Mechanical Equivalent
  2 FF Synchronisation, Metastability
  Metastability Probability, Mean Time between Failures
  Synchronisation using Handshake Protocol or FIFO
• Finite State Machines
  FSM Specification, Flow Table, State Graph
  Mealy/Moore FSMs, Encoding, Implementing FSMs using Binary Logic
  Initialisation, Determinism, Don’t Cares
  Interacting FSMs, Multiple FSM Composition
  Equivalent States, K-distinguishable and K-equivalent states
  State Minimisation for Fully-Specified FSMs, Minimisation with DCs
• Boolean Algebra, Boolean Optimisation
  Function Representation on the Binary Cube
  Boole/Shannon Expansion, Canonical Forms, Minterms/Maxterms
  Consensus, Implication, the SAT problem, SDCs/ODCs
  Tautology, Implicants and Prime Implicants
  Essential Implicants, Quine/McCluskey Theorem
  Primes Computation using Tabular Method, the Unate Covering Problem
  Minimisation with Don’t Cares, Multiple Output Functions
• Timing, Stating Timing Analysis
  Combinational Gate Delay, Sequential Gate Delay, Setup and Hold Constraints
  Synchronous Circuit Model – Path Types, Static Timing Analysis
  Minimum Period, Hold Violations, Clock Tree Design
  Clock Gating

The goals of HY430, “Digital Systems Lab”, include (1) gaining an understanding in the theoretical fundamentals of Digital System design, (2) getting accustomed to practical design and implementation methodologies, particularly focusing on programmable logic and FPGAs (Field Programmable Gate Arrays) and the Verilog Hardware Description Language, and (3) the combination of theory and practice in implementing and testing useful and practical circuits in the laboratory, where students use cutting edge FPGA development boards.

The course focuses on providing equilibrium between theoretical knowledge and hands-on practice for the design of realistic digital circuits of small or medium size. Thus, in combination with the necessary presented theoretical background in digital design, which includes: (a) Boolean algebra fundamentals, basic gates, number representation, Boolean algebra Axioms and Identities, (b) combinational circuits, representation and analysis, 2-level and multi-level implementation, Area-Delay Pareto curve, (c) Sequential circuits, registers, latches, analysis of circuits with feedback, (d) SRAM/DRAM memories, (e) busses, (f) timing and synchronization of digital circuits, the theory background is combined state of the art FPGA implementation flows and the Verilog Hardware Description Language. State of the art FPGA boards, in conjunction with the appropriate EDA (Electronic Design Automation) software are presented and used, not only for simulation, but also for implementation in the course laboratory, where lab assignments are implemented on the FPGA devices and tested.

Upon successful completion of the course, the student will possess the following understanding and skill set:

• Knowledge and Understanding of the theory of Digital Systems Design
• Knowledge and Understanding of practical, commercial EDA tools for FPGA design
• Understanding of the methodology for describing circuits in Verilog HDL for synthesizability by EDA tools
• Extensive Practice on the theory and the implementation methodology from the completion of the 4 Labs of the course, by implementing a set of practical digital circuits as well as testing them. For the successful completion of the labs, analysis of the circuit specifications is required, synthesis of the required subcomponents, as well as quantification of the optimal synthesis
• Knowledge of writing up Technical Manuals describing their circuit implementations, which describe the design, verification and test process.