ECE425 Testing and Verification of Digital Circuits

• Formal verification problem.
• Formal verification Languages.
• Binary Decision Diagrams (BDD), Reduced Ordered BDD (ROBDD).
• Model Checking
• Satisfiability checker.
• Bounded Model Checking
• Formal Equivalence Checking.
• Fault modeling
• Fault simulation
• Combinational and Sequential ATPG
• Design for test, Scan Design and Boundary scan standard

The main objectives of the course are:

• To have a theoretical understanding of popular integrated circuits (IC) testing and formal verification algorithms.
• To be able to incorporate appropriate testing & verification techniques into various phases of VLSI development.
• To understand the usage of test and verification EDA software tools and their integration in a global design-flow.
• To understand the necessity of VLSI testing and verification and to know standard methods applied in VLSI design.
• To be able to apply appropriate testing methods in various phases of VLSI developments.