| Subject Area | Computer Hardware and Architecture |
|---|---|
| Semester | Semester 8 – Spring |
| Type | Elective |
| Teaching Hours | 4 |
| ECTS | 6 |
| Recommended Courses |
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| Course Site | https://eclass.uth.gr/courses/E-CE_U_104 |
| Course Director |
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| Scientific Responsible | Stamoulis Georgios, ProfessorE-mail: georges@uth.gr |
|---|---|
| Title | Hellenic Chips Competence Centre (HCCC) |
| Funding Agency | Το HCCC υποστηρίζεται από το Chips JU και τα μέλη του, και συγχρηματοδοτείται από την Ευρωπαϊκή Ένωση και την Ελληνική Κυβέρνηση μέσω του προγράμματος “Ανταγωνιστικότητα” |
| Budget | 326.350,00 |
| Duration | 01/06/2025 – 31/05/2029 |
| Scientific Responsible | Plessas Fotios, ProfessorE-mail: fplessas@uth.gr |
|---|---|
| Title | Αναλογικός Σχεδιασμός, Δοκιμές και Επαλήθευση |
| Funding Agency | NanoZeta Technologies ltd. |
| Budget | 271.400,00 |
| Duration | 26/01/2021 – 25/01/2028 |
| Scientific Responsible | Korakis Athanasios, ProfessorE-mail: korakis@uth.gr |
|---|---|
| Title | DIGITAfrica: Towards a comprehensive pan-African research infrastructure in Digital Sciences |
| Funding Agency | ΕΥΡΩΠΑΪΚΗ ΕΝΩΣΗ |
| Budget | 123.125,00 |
| Duration | 16/12/2024 – 31/12/2027 |
| Department of Electrical and Computer Engineering | |
|---|---|
| |
| Tel. | +30 24210 74967, +30 24210 74934 |
| gece ΑΤ uth.gr | |
| PGS Tel. | +30 24210 74933 |
| PGS e-mail | pgsec ΑΤ uth.gr |
| URL | https://www.e-ce.uth.gr/contact-info/?lang=en |
| Subject Area | Computer Hardware and Architecture |
|---|---|
| Semester | Semester 8 – Spring |
| Type | Elective |
| Teaching Hours | 4 |
| ECTS | 6 |
| Recommended Courses |
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| Course Site | https://eclass.uth.gr/courses/E-CE_U_104 |
| Course Director |
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| Course Instructor |
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The goals of HY4xx include gaining understanding, insight and familiarization with state-of-the-art EDA (Electronic Design Automation) Physical Design Algorithms, and automated flows for the physical realization of a synthesized netlist.
The course focuses on the automatic, standard-cell physical layout design for ASIC designs, and related algorithms for (1) Circuit Partitioning, (2) Floorplanning, (3) Placement, (4) Routing and (5) Clock tree design. The course presents a set of both exact and heuristic algorithms similar to those implemented in commercial tools.
Upon successful completion of the course, students will be accustomed with the following concepts and skill sets:
